Multimodal optimization technique in test generation
US6810372B1 · kind B1 · utility
21Cited by
2References
12Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 7, 1999 |
| Grant date | Oct 26, 2004 |
| Priority date | — |
| Expiry date | Dec 7, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318371
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of and system for generating tests and using the tests to identify VLSI simulation and circuit operation faults and errors and validate performance uses a genetic algorithm. Each generation of tests is further processed to eliminate redundant tests and make room for the insertion of new genetic material into the population in the form of random test vectors. The resulting family of tests generated using a simulation of the VLSI can then be ported to the circuit once prototyped in silicon and adapted to the new environment using, once again, the genetic algorithm to suitably evolve the test population.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.