Method and apparatus for modeling using a hardware-software co-verification environment
US6810373B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2000 |
| Grant date | Oct 26, 2004 |
| Priority date | — |
| Expiry date | Nov 20, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for modeling using a hardware-software software co-verification environment is provided. An instruction set simulator is coupled to a simulator circuit to determine if the hardware design is correct. Specifically, the instruction set simulator acts as a “master” to the simulator circuit, thus providing a faster simulation environment. The simulator circuit contains a bus functional model, a hardware model, transfer memory, and the hardware design to be tested. The hardware model is designed to emulate a micro-controller. By disabling a processor within the hardware model, the speed of the simulation is restricted only by the speed of the instruction set simulator or the hardware design. Furthermore, the hardware design may be uncoupled from the simulator circuit in order to initialize the operating system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.