Bus arbitration system and method for carrying out a centralized arbitration with independent bus request and grant lines
US6810455B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 28, 2001 |
| Grant date | Oct 26, 2004 |
| Priority date | — |
| Expiry date | Feb 19, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a bus arbitration system and method which assume that each operation using the bus requires from one to five bus clock cycles. Each potential bus master has a dedicated bus request line and a dedicated bus grant line, both of which are connected to a centralized bus arbiter in the bus arbitration system of the present invention. When a potential bus master wants to use the bus for, for instance, three bus clock cycles, the bus master activates its dedicated bus request line for the same number of bus clock cycles as it would need of bus use (i.e. three bus clock cycles). This three clock wide bus request pulse is recorded in a bus request recording circuit in the centralized bus arbiter. Access to the bus can be granted by the centralized bus arbiter to a winning bus master under any bus arbitration policies. If a potential bus master is chosen to be the winning bus master, the centralized bus arbiter activates the winning bus master's dedicated bus grant line for the same number of bus clock cycles as requested by the bus master, i.e. for three bus clock cycles. So, the bus master will have sufficient use of the bus for its desired operation. After that, the arbiter c…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.