Multiprocessor computer system for processing communal locks employing mid-level caches
US6810464B1 · kind B1 · utility
6Cited by
18References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2001 |
| Grant date | Oct 26, 2004 |
| Priority date | — |
| Expiry date | Aug 1, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S707/99938
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Multi-processor computer systems with multiple levels of cache memories are given an alternate pathway for handling highly contended-for locks. These are called communal locks. The alternate pathway allows for alternate processing schemas that do not impede the performance of the overall system as is otherwise the case in such computer systems where contended-for locks bounce back and forth between contending caches, crimping storage bus bandwidth and system performance. The alternative pathway is not used for ordinary (non communal software lock) data and instruction transfers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.