Iteractive decoder employing multiple external code error checks to lower the error floor
US6810502B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2001 |
| Grant date | Oct 26, 2004 |
| Priority date | — |
| Expiry date | Dec 3, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0066
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Iterative decoder employing multiple external code error checks to lower the error floor and/or improve decoding performance. Data block redundancy, sometimes via a cyclic redundancy check (CRC) or Reed Solomon (RS) code, enables enhanced iterative decoding performance. Improved decoding performance is achieved during interim iterations before the final iteration. A correctly decoded CRC block, indicating a decoded segment is correct with a high degree of certainty, assigns a very high confidence level to the bits in this segment and is fed back to inner and/or outer decoders (with interleaving, when appropriate) for improved iterative decoding. High confidence bits may be scattered throughout inner decoded frames to influence other bit decisions in subsequent iterations. Turbo decoders typically operate relatively well at regions where the BER is high; the invention improves iterative decoder operation at lower BERs, lowering the ‘BER floor’ that is sometimes problematic with conventional turbo decoders.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.