Process for forming a low resistivity titanium silicide layer on a silicon semiconductor substrate
US6812121B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 16, 2001 |
| Grant date | Nov 2, 2004 |
| Priority date | — |
| Expiry date | May 16, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0223
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for forming a low resistivity titanium silicide layer on the surface of a silicon semiconductor substrate. In the process, an effective amount of a metallic element such as indium, gallium, tin, or lead is implanted or deposited on the surface of the silicon substrate. A titanium layer is deposited on the surface of the silicon substrate, and a rapid thermal annealing of the titanium-coated silicon substrate is performed to form low resistivity titanium silicide. In preferred processes, the metallic element is indium or gallium, and more preferably the metallic element is indium. A semiconductor device that has a titanium silicide layer on the surface of a silicon substrate is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.