Integrated circuit with a reduced risk of punch-through between buried layers, and fabrication process
US6812541B2 · kind B2 · utility
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25Claims
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Key dates
| Filing date | Dec 2, 2003 |
| Grant date | Nov 2, 2004 |
| Priority date | — |
| Expiry date | Dec 2, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The semiconductor substrate of the integrated circuit includes at least one dielectrically isolating, vertical buried trench (2) having a height at least five times greater than its width, the trench laterally separating two regions (4, 5), and an epitaxial semiconductor layer (6) coveting the trench. An application is advantageously suited to MOS, CMOS and BiCMOS technologies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.