Wafer scale package and method of assembly
US6812558B2 · kind B2 · utility
3Cited by
4References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2003 |
| Grant date | Nov 2, 2004 |
| Priority date | — |
| Expiry date | Jun 19, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A plurality of electronic circuits and associated signal lines are positioned at respective locations on a base wafer. A cover wafer, which fits over the base wafer, includes a corresponding like number of locations each including one or more cavities to accommodate the electronic circuit and associated signal lines. The cover wafer includes a plurality of vias for making electrical connection to the signal lines. A multi layer metallic arrangement hermetically seals the periphery of each location as well as sealing the bottom of each via. The joined base and cover wafers may then be diced to form individual die packages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.