Fanned out interconnect via structure for electronic package substrates
US6812576B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 2002 |
| Grant date | Nov 2, 2004 |
| Priority date | — |
| Expiry date | May 14, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/096
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An interconnect via structure according to the present invention can be used to support high frequency broadband signal transmission. The interconnect vias progressively increase in size and pitch from the signal source layer of the package substrate to the terminal pad layer of the package substrate. Each interconnect via includes a plurality of conductive sections formed at different substrate layers. At each substrate layer, the size and pitch of the vias result in a specified impedance. In a practical embodiment, the via impedance at each substrate layer is constant (e.g., 50 ohms). The interconnect structure can maintain a constant impedance while transitioning from a relatively narrow pitch at the signal source layer to a relatively wide pitch at the terminal layer, which may correspond to the pitch of the package substrate solder balls.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.