Method for driving a power semiconductor
US6812772B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2002 |
| Grant date | Nov 2, 2004 |
| Priority date | — |
| Expiry date | Oct 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/105
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The integrated gate dual transistor (IGDT) has two controllable gates (G1, G2), a first gate (G1) being provided on the cathode side and being driven via a low-inductance first gate terminal with a first gate current, and a second gate (G2) being provided on the anode side and being driven via a low-inductance second gate terminal with a second gate current. In the switch-off operation of the IGDT, the rate of rise of the voltage across the IGDT is limited via the two gates. Limiting the rate of rise of the voltage across the IGDT prevents voltages from building up at different speeds in a series circuit of IGDTs, and thus unequal loads from overheating and destroying the individual IGDTs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.