Phase-locked loop with loop select signal based switching between frequency detection and phase detection
US6812797B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2003 |
| Grant date | Nov 2, 2004 |
| Priority date | — |
| Expiry date | May 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/14
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop (PLL) includes at least first and second loops, and loop selection circuitry coupled to the first and second loops, the loop selection circuitry being responsive to at least one loop select signal to control transition from an operating mode of one of the first and second loops to an operating mode of the other of the first and second loops. In an illustrative embodiment, the PLL comprises a dual-loop PLL with the first and second loops corresponding to respective frequency and phase loops, and the loop selection circuitry is configured such that the loop select signal as applied to a control input of a current-generating component of the first loop represents a delayed and inverted version of the loop select signal as applied to a control input of a current-generating component of the second loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.