Current integrating sense amplifier for memory modules in RFID
US6813209B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2003 |
| Grant date | Nov 2, 2004 |
| Priority date | — |
| Expiry date | Oct 14, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A low read current, low power consumption sense amplifier well suited for low frequency RFID systems is disclosed. An MOS transistor receives the read current from a memory cell, typically an EEPROM, and a current mirror is formed by a parallel MOS transistor. The mirror current is integrated on a capacitor after the charge on the capacitor is cleared via a reset pulse. A time period is defined during which the voltage on the capacitor is compared to a second voltage. The second voltage is formed from a reference voltage or from dummy cells, in either case the reference voltage is at about the logic boundary between a one and zero stored in a memory cell. A comparator, with or without input hysteresis, receives the voltage on the capacitor and a second voltage and within the time period, the output state of the comparator indicates the binary contents of the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.