Digital demodulator
US6813321B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2000 |
| Grant date | Nov 2, 2004 |
| Priority date | — |
| Expiry date | Jul 21, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0095
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital demodulator which will need no absolute phasing circuit is provided. A known-pattern BPSK signal generating circuit 6 generates the same known-pattern BPSK signal as a known-pattern BPSK signal in a received digital modulated wave in synchronism with the known-pattern BPSK signal in the received digital modulated wave, a carrier-reproducing phase error detecting circuit 7 has a phase error table where one of reference phases in a signal point position of a demodulation baseband signal is made a convergence point, a phase error voltage corresponding to a phase error between a phase determined from the signal point position of the demodulation baseband signals and a phase convergence point is sent out, by enable-controlling a carrier-reproducing loop filter 8 according to the known-pattern BPSK signal outputted from the known-pattern BPSK signal generating circuit 6, the phase error voltage is smoothed, and carrier reproduction is performed while controlling the frequency of a reproduced carrier according to the smoothed output so that the phase in the signal point position coincides with the phase convergence point.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.