Efficient memory structure simulation for sequential circuit design verification
US6813599B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2000 |
| Grant date | Nov 2, 2004 |
| Priority date | — |
| Expiry date | Mar 22, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for efficiently simulating memory structures of a sequential circuit for design verification of the sequential circuit. The method is implemented by an computer system having a processor coupled to a memory via a bus, the memory storing computer readable code which when executed by the processor cause the computer system to perform the steps of the memory structure simulation method. The method includes accessing a netlist description of a sequential circuit, wherein the description is for realizing the sequential circuit in a physical form. Memory elements included within the description are identified. For these memory elements, inputs to the memory elements and outputs from the memory elements are identified. Using this information, the memory elements are grouped into at least one group of functionally related memory elements. Subsequently, the memory elements of the one or more groups are collectively addressed as a group. Similarly, data for the memory elements of the one or more groups are collectively written as a group. Once written, the data is coupled to circuit elements within the description that are coupled to the outputs of the memory elements such that the …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.