Method and apparatus for performing equality comparison in redundant form arithmetic
US6813628B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2000 |
| Grant date | Nov 2, 2004 |
| Priority date | — |
| Expiry date | Jan 31, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/4824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus is disclosed to compare numbers for equality. The numbers represented in a redundant form, including numbers received from a bypass circuit are subtracted.More specifically, a complemented form is generated and supplied to an arithmetic circuit for at least one number represented in the redundant form. Input to the arithmetic circuit is adjusted to augment a result generated through the arithmetic circuit to generate a valid outcome represented in the redundant form as a result of a subtraction operation. Results of the subtraction operation are compared to zero in redundant form using a non-propagative circuit and without requiring carry propagation, thereby producing an equality comparison of the number in redundant form.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.