Dual-edge fifo interface
US6813674B1 · kind B1 · utility
37Cited by
36References
6Claims
0Family size
Assignee
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Key dates
| Filing date | May 12, 2000 |
| Grant date | Nov 2, 2004 |
| Priority date | — |
| Expiry date | May 12, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual-edge FIFO interface having a host FIFO interface operative to receive data from a host module on a single edge of a host clock, and determine situations when valid read data is present in a read data FIFO or when the read data FIFO is full, a target FIFO interface operative to receive read data from a target core module, transfer data out, and determine when the read data FIFO is full, and a register block in communication with the host FIFO and the target FIFO, wherein the dual-edge FIFO interface is operative to interconnect internal modules at a core logic level, a block level, or a chip level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.