Flash memory system
US6813678B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2000 |
| Grant date | Nov 2, 2004 |
| Priority date | — |
| Expiry date | Sep 6, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system (10) comprising a non-volatile memory (18) having memory locations (38), and a controller (16) for writing data structures to and reading data structures from the memory. The system (10) is architecturally configured so that the locations (38) can be written to individually but are erasable only in blocks. The controller (16) forms one or more erasable units (39) which are each subdivided into cells (50) each consisting of a group of locations (38). The controller (16) writes data structures to and reads structures from each cell (50) on a per cell basis. The system (10) may comprise a controller (16) embedded in a FLASH memory card. Alternatively, the controller (16) may be embedded in, or implemented in, a host system such as a Personal Computer (PC).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.