Memory disambiguation scheme for partially redundant load removal
US6813705B2 · kind B2 · utility
81Cited by
5References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 5, 2001 |
| Grant date | Nov 2, 2004 |
| Priority date | — |
| Expiry date | Dec 1, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An optimization scheme used at run-time or compile-time is capable of identifying partially redundant loads and determining whether the load is truly redundant. The truly redundant load may be replaced with a register copy instruction to reduce the memory traffic and save CPU cycle time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.