Control unit having a main microprocessor and having a processor interface to a bus transceiver unit

US6813727B2 · kind B2 · utility

Assignee

• Bayerische Motoren Werke Aktiengesellschaft · DE

Inventors

• Joachim Froeschl · Herrsching am Ammersee, DE
• Josef Krammer · Holzkirchen, DE
• Anton Schedl · Munich, DE

Key dates

• Filing date: Jun 20, 2001
• Grant date: Nov 2, 2004
• Expiry date: Nov 26, 2022

Classification

• Technology area (CPC G): Physics
• CPC primary: G05B2219/24043
• WIPO field: Control
• WIPO sector: Instruments

Abstract

A control unit has a main microprocessor and processor interface to a bus transceiving unit, which has at least one transmit memory, one receive memory and one bus controller. Devices are provided by which the data content of the transmit memory and/or of the receive memory is reset to a defined status after each output and/or reading-in of the data stored in either memory, and before the main microprocessor outputs and/or reads in new data.