Address counter test mode for memory device
US6813741B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2000 |
| Grant date | Nov 2, 2004 |
| Priority date | — |
| Expiry date | May 18, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory having a circuit including a built-in address counter with a test mode. The address counter may be used to generate the memory array addressing for the different array test patterns. The circuit may comprise a logic circuit and a counter circuit. The logic circuit may be configured to generate one or more control signals in response to one or more control inputs. The counter circuit may be configured to generate a first counter output and a second counter output in response to (i) the control outputs and (ii) one or more inputs. The counter may comprise a first portion configured to generate the first counter output and a second portion configured to generate the second counter output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.