Chip scale package, printed circuit board, and method of designing a printed circuit board
US6815621B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2001 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | Mar 6, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10734
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip scale package has first and second sets of external signal terminals arranged in rows and columns at respective sides of the bottom surface of the package The spacing between the rows of the first set of signal terminals is greater than the spacing between the rows of the second set of signal terminals. The chip scale packages are mounted to and integrated by a printed circuit board having corresponding lands in each of a plurality of chip scale package regions. Thus, the spacing between adjacent rows of a first set of lands is greater than the spacing between adjacent rows of a second set of lands. The rows of the first lands are spaced wider apart so that a plurality of first signal lines can extend contiguously between each adjacent pair of rows of first lands, in each of the chip scale package regions. A method of designing the printed circuit board lays out the lands of the PCB in rows and columns, sets the spacing thereof, and traces out the signal lines. The signal lines of the printed circuit board are arranged efficiently so that the number of the layers of the printed circuit board necessary for accommodating the lines can be minimized, and the production costs the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.