Gate feed structure for reduced size field effect transistors
US6815740B2 · kind B2 · utility
8Cited by
2References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 29, 2002 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | Jun 20, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A FET or BJT structure or distributed transistor amplifier having a tapered gate feed line and a tapered channel width (tapered source fingers, tapered drain fingers) provides increased bandwidth and gain in the microwave/mm-wave frequency spectrum.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.