Sequential control circuit
US6815842B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2001 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | Oct 30, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05B47/184
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A control circuit for driving a plurality of electrical loads, one at a time, has a converter circuit for receiving a DMX compatible digital control signal and extracting a plurality of address bits therefrom. A decoder circuit receives the digital address bits and generates a plurality of enable signals, each corresponding to a particular load. One of the load enable signals is in an active state and each other enable signal is in an inactive state at any one time. A relay circuit for receives the enable signals, and in response passes an electrical drive signal to the electrical load corresponding to the enable signal that is in the active state. The relay circuit preferably includes a plurality of relay devices each coupled to one of the enable signals and a plurality of discharge circuits for rapidly discharging each electrical load when the enable signal corresponding to that load changes from the active state to the inactive state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.