Phase locked loop
US6815987B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2002 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | Nov 2, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop (PLL), which has high operation speed and high resolution, and is particularly applicable in high frequency process, is disclosed. The PLL, receiving a data signal and generating a clock signal, comprises a voltage controlled oscillator (VCO) and multi-phase generator (MPG), a transition detector, an optimal phase encoder, and a phase selector, wherein the four devices are respectively used for outputting N phase clock signals of same frequency but different phases, for outputting a data period value and a clock period value by receiving the N phase clock signals, the data signal and the clock signal, for outputting a phase select signal according to the data period value and the clock period value, and for outputting one of the phase clock signals according to the phase select signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.