Delay locked loops having blocking circuits therein that enhance phase jitter immunity and methods of operating same
US6815990B2 · kind B2 · utility
11Cited by
18References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 24, 2003 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | Apr 24, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/095
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.