Minimizing noise in data channels implemented using frequency division multiplexing
US6816004B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2002 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | Oct 12, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/126
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A filter circuit with two 2nd order stages cascaded in sequence. The first stage is implemented with high quality (Q) factor, and the second stage is implemented with a low Q factor and an imaginary zero. The first stage is designed to further eliminate the unwanted frequency components. The imaginary zero in the second stage eliminates the noise present in the output of the first stage due to the requirement of high Q in the first stage. Any additional noise introduced by the second stage is minimal due to the low Q of the second stage. Each stage may be implemented using only a single operational amplifier when the first stage generates a differential output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.