Data line drive circuit for panel display with reduced static power consumption
US6816144B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 13, 2001 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | Sep 11, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/027
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A data line drive circuit for a liquid crystal display comprises a selection circuit 20 receiving from a D/A converter 16 a plurality of voltages V1 to V3 corresponding to data lines 301 to 303 of the liquid crystal display, for outputting a selected one of the received voltages, an analog buffer 22A connected to an output of the selection circuit, a distribution circuit 24 receiving an output of the analog buffer for selectively distributing the output of the analog buffer to a selected one of the data lines, and a precharge circuit 26 for precharging each of the data lines to either VDD or VSS in accordance with at least the most significant bit of the corresponding digital data, during a precharge period at the beginning of each scan line selection period. During a first writing period succeeding to the precharge period, a voltage V1 corresponding to the data line 301 is supplied to the analog buffer 22A, and the output of the analog buffer is supplied to the data line 301. During a succeeding and second writing period, a voltage V2 corresponding to the data line 302 is supplied to the analog buffer 22A, and the output of the analog buffer is supplied to the data line 302.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.