Packet synchronization detector
US6816560B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 5, 2000 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | Jul 29, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/70
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A packet synchronization detector for an incoming digital signal which includes a regularly repeated predetermined synchronization pattern which repetition rate defines the length of one transmission packet according to the present invention comprises a synchronization pattern detector (1) and several synchronization state machines (2, 31, . . . , 3n) which respectively determine whether or not one detected synchronization pattern with a respective position in regard to the length of one transmission frame has the correct repetition rate to determine whether or not lock has been achieved. Therefore, a very fast lock is achieved, since also in case of bit patterns that match to the synchronization byte, but that are not the synchronization byte no penalty time occurs to lock to the incoming digital signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.