Phase correction for multiple processors
US6816561B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 4, 2000 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | May 28, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for processing data includes a first processor and a second processor. The first processor receives a source clock signal and converts the source clock signal to a first timing signal with a first phase. The second processor receives the source clock signal and converts the source clock signal to a second timing signal with a second phase. A phase connection circuit coupled to the first processor and the second processor determines whether the first phase is equivalent to the second phase. If the first phase and the second phase are not equivalent, the first processor will modify the first phase such that the first phase and the second phase are equivalent. The first processor may modify the first phase by inverting the first timing signal or by adding a clock delay to the first timing signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.