Silicon object array with unidirectional segmented bus architecture
US6816562B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2003 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | Apr 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17732
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A logic array is provided, which includes a plurality of unidirectional segmented buses connecting a plurality of processing elements, called silicon objects, within an integrated circuit. The bus includes a string of unidirectional bus segments. Each silicon object includes a bus input coupled to one of the bus segments in the first bus, and a bus output coupled to a next subsequent one of the bus segments in the first bus. A landing circuit is coupled to the bus input for receiving digital information from the bus input. A function-specific logic block is coupled to an output of the landing circuit and has a result output. Each silicon object further includes a multiplexer having first and second inputs coupled to the bus input and the result output, respectively, and having an output coupled to the bus output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.