Method for statically timing SOI devices and circuits
US6816824B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 1999 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | Apr 19, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Low-conductance and high-conductance IV characteristics (models) are created using the low and high end of their body voltage ranges, respectively. The body voltage of the device (FET) is initialized to the low end of range at time zero, and then a transient, two dimensional sweep of gate and drain voltages is performed. Drain currents are measured in this two dimensional region and are used to create a piecewise, linear IV model of device. The process is repeated for the highest body voltage. This process differs significantly from prior art bulk device characterization techniques, which did not have to initialize body voltage or perform a transient analysis. The body voltage is modulating during the switching event due to the gate-to-body and diffusion-to-body coupling; and thus only a transient analysis can properly model these coupling effects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.