Delay correlation analysis and representation for vital complaint VHDL models
US6817000B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 2, 2002 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | Jul 18, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system unbind a rise/fall tuple of a VHDL generic variable and create rise time and fall time generics of each generic variable that are independent of each other. Then, according to a predetermined correlation policy, the method and system collect delay values in a VHDL standard delay file, sort the delay values, remove duplicate delay values, group the delay values into correlation sets, and output an analysis file. The correlation policy may include collecting all generic variables in a VHDL standard delay file, selecting each generic variable, and performing reductions on the set of delay values associated with each selected generic variable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.