Method of design and fabrication of integrated circuits using regular arrays and gratings
US6818389B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2001 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | Apr 8, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/70466
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A circuit fabrication and lithography process utilizes a mask including dense repetitive structures of features that result in a wide array of fine densely populated features on the exposed substrate film. Following this, a trimming procedure is performed to remove any unwanted fine patterned features providing multiple trimmed patterns on the substrate. An optional final step adds additional features as well as the interconnect features thus forming a circuit pattern. In this manner, all fine features may be generated using the exact same density of intensity patterns, and therefore, maximum consistency between features is established without the need for optical proximity correction. The secondary exposures are substantially independent from the initial dense-feature exposure in that the exposure of one set of features and the subsequent exposure of another set of features result in separate independent resist or masking layer reactions, thus minimizing corner rounding, line end shortening and other related spatial frequency effects and unwanted exposure memory effects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.