Method of electronic component fabrication and an electronic component
US6818486B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 31, 2003 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | Mar 31, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K85/113
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating an electronic component is disclosed in which an electrically conductive layer (4) is provided upon a substrate (2). A mask (6) having a window (8) is provided upon the layer and by etching, preferably chemically, through the window an opening (10) the conductive layer. Conductive material is deposited, preferably by vapor deposition, through the window to form an island in the opening. The etching of the conductive layer is carried out such that the conductive layer is undercut at the periphery of the window with the result that the periphery of the island is spaced apart from the periphery of the opening. Also disclosed is a thin film transistor structure well suited to fabrication by the above described method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.