Non-volatile memory device to protect floating gate from charge loss and method for fabricating the same
US6818511B2 · kind B2 · utility
7Cited by
4References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 23, 2003 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | Oct 23, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
Disclosed are a non-volatile memory device to protect a floating gate from charge loss and a method for forming the same. At least a pair of floating gate lines are formed on a semiconductor substrate. A portion of the substrate between the floating gate lines is etched to form a trench therein. A gap-fill dielectric layer is formed in the trench and also in the gap between the pair of floating gate lines. The gap-fill dielectric layer is implanted with impurities so that positive mobile ions that may permeate the floating gate through the gap-fill dielectric layer can be trapped in the gap-fill dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.