Thin film transistor array substrate and manufacturing method thereof
US6818923B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2002 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | Oct 23, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136236
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A thin film transistor array substrate, and its manufacturing method, that is made using a three-round mask process. Gate patterns, each of which includes a gate line consisting of a transparent metal pattern and a gate metal pattern, a gate electrode, a lower gate pad, a lower data pad, and a pixel electrode are formed using a first mask process. A second mask process forms a gate insulating pattern and a semiconductor pattern. A third mask process forms source and drain patterns, each of which includes a data line, a source electrode, a drain electrode, an upper gate pad and an upper data pad. Additionally, the gate metal pattern on an upper portion of the pixel electrode is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.