Semiconductor device and method of manufacturing the same
US6818995B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 16, 2003 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | Jan 16, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7681
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A Cu wiring member containing Cu as the main component is embedded in an interlayer dielectric film among multiple wiring layers accompanied with a coating of a barrier metal and an upper diffusion barrier layer formed thereon. The interlayer dielectric film is composed of a first dielectric film that forms a major part thereof and a second dielectric film that is provided adjacent to the first dielectric film and forms side walls of the Cu wiring member. The first dielectric film and the second dielectric film have mutually different etching selection ratios. When a wiring layer in an upper layer is connected to the Cu wiring member through the via hole VH formed in the first dielectric film by etching, a substantial matching margin can be expected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.