Dividing and distributing the drive strength of a single clock buffer
US6819138B2 · kind B2 · utility
3Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2002 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | Feb 20, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Devices, methods, and networks that divide and proportionally distribute the drive strength of a clock buffer such that the output drive strength of the clock buffer is divided proportionally among a plurality of outputs from the clock buffer. In one embodiment, the present invention selectively couples adjacent parallel inverters present in a clock buffer to separate, internal distribution wires. The internal distribution wires are selectively coupled to one or more outputs by a connector wire to provide proportional, multiple outputs of the drive strength from the clock buffer to a clock network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.