High speed, static digital multiplexer
US6819141B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2000 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | Mar 14, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/693
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high speed static multiplexer comprising: (1) a plurality of data inputs and at least one select input; (2) an output; (3) a high voltage rail and a low voltage rail; (4) a pull-up circuit coupled between the output and the high voltage rail and further coupled to receive the data inputs and the select input so that the pull-up circuit generates a first logic state at the output in response to the selected data input having that first logic state; (5) and a pull-down circuit coupled between the output and the low voltage rail and further coupled to receive the data inputs and the select input, so that the pull-down circuit generates a second logic state at the output in response to the selected data input having that second logic state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.