Memory interleaving technique for texture mapping in a graphics system
US6819324B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 11, 2002 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | Oct 13, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2200/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A graphics system and method for storing and accessing texture maps comprising texels. The graphics system may include a graphics processor and a texture memory comprising a plurality of memory devices for storing the texture maps. The texels (or portions of the texels) may be stored in the memory devices in an interleaved fashion. The texel data is interleaved in the memory devices to guarantee that, no matter which N×M array of texels is accessed, each texel in the array is present in a different memory device or chip and hence are concurrently available. Thus the N×M array of texels may be output concurrently or simultaneously, regardless of which array is accessed, i.e., regardless of which pixel is addressed. Embodiments are also described where the memory devices output arrays of texels for at least two respective neighboring pixels, or a 3D array of texels, in parallel in response to a single read transaction. Also, the body and border portions of the texture map are stored in separate areas of memory (e.g., in different memory address spaces), but texel interleaving is still performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.