Viterbi decoder and Viterbi decoding method
US6819724B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2000 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | Dec 12, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6343
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A data estimating circuit outputs estimation data which estimates input data at a time earlier by a predetermined bit cycle than the input data based on decoded data series outputted from a path memory. A target value computing circuit corrects the target value with a difference between the estimation data and input data as a target value error and outputs obtained plural first target values to a branchmetric operating circuit as plural target values. Because the branchmetric operating circuit can conduct branchmetric operation based on plural first target values near plural averages having the highest incidence (having peaks in histogram), decoding performance can be improved more as compared to using fixed target values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.