Context based cache indexing
US6820170B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2002 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | Dec 26, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1009
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Multiple attempts are made to identify an entry in a cache. For example, a first attempt uses a RAM-based addressing structure (such as the above-described table) and a second attempt (on failure of the first attempt) uses a CAM-based addressing structure. The RAM-based addressing structure is faster than the CAM based-addressing structure, and in cases of a hit on the first attempt, cache performance is based on RAM cycle time rather than CAM cycle time. On the other hand, a miss on the first attempt does not mean that the data is not present in the cache. Instead, a second attempt using the CAM in the traditional manner finds the data if present in the cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.