Computation core executing multiple operation DSP instructions and micro-controller instructions of shorter length without performing switch operation
US6820189B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2000 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | May 12, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computation core for executing programmed instructions includes an execution block for performing digital signal processor operations in response to digital signal processor instructions and for performing microcontroller operations in response to microcontroller instructions, a register file for storing operands for and results of the digital signal processor operations and the microcontroller operations, and control logic for providing control signals to the execution block and the register file in response to the instructions. The digital signal processor instructions each have a first length and the microcontroller instructions each have a second length that is less than the first length.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.