Power managed graphics controller
US6820209B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2000 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | May 8, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A controller (or controller chip) providing reduced power consumption without impacting performance is disclosed. The controller monitors activity of components within the controller which require access to a local memory, and then decreases a clocking frequency for a memory interface to the local memory when the monitoring indicates that reduced amounts of activity are present. Following such a decrease in the clocking frequency, when increased amounts of activity are detected, the clocking frequency is increased for high performance operation. The controller thus tailors the clocking frequency for the memory interface in accordance with the amount of activity of these components that require access to the local memory so that overall less power is used by the controller yet the performance is essentially not hindered. In one embodiment, the controller is a graphics controller, as such controllers require access to local memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.