Device and method for detecting errors in CRC code having reverse ordered parity bits
US6820232B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2001 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | Dec 10, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/09
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A device for detecting in a receiver whether any transmission errors have occurred in the received CRC code, in a case that a transmitter transmits the CRC code created by sequencing the parity bits, which are generated using the generator polynomial, in the reverse order and appending them to the message bits. The device comprises a division unit for dividing the message bits by the parity bit generator polynomial to form the remainder, a comparison unit for bitwise comparing the remainder bits with the reverse ordered parity bits, and a decision unit for deciding whether transmission errors have occurred in the CRC code based on the results of the comparison unit. According to the present invention, the transmission errors in the received CRC code are effectively detected, when the CRC code includes the parity bits sequenced in the reverse order, unlike the conventional normal order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.