Mechanism for software pipelining loop nests
US6820250B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2002 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | May 9, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/4452
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided for processing nested loops that include a modulo-scheduled inner loop within an outer loop. The nested loop is scheduled to execute the epilog stage of the inner loop for a given iteration of the outer loop with the prolog stage of the inner loop for the next iteration of the outer loop. For one embodiment of the invention, this is accomplished by initializing an epilog counter for the inner loop to a value that bypasses draining the software pipeline. This causes the processor to exit the inner loop before it begins draining the inner loop pipeline. The inner loop pipeline is drained during the next iteration of the outer loop, while the inner loop pipeline fills for the next iteration of the outer loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.