Solderless test interface for a semiconductor device package
US6820794B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 27, 2002 |
| Grant date | Nov 23, 2004 |
| Priority date | — |
| Expiry date | Jan 16, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10734
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A solderless test interface (10) includes a thin, flexible, electrically insulative sheet (20) having metal plated through-holes (24) formed in the pattern of the external ball contacts (54) of a semiconductor device (14). The termini (26, 30) of the holes (24) on the surface of the sheet (20) are also plated. The metal (40) is coated with a soft metal (42) which will cold-flow under force. The sheet is inserted between the ball contacts (54) and a test board (18). Force is applied to the test board and/or the device to engage and deform the soft metal (42) at the hole termini (26, 30) by its engagement with the balls (54) and pads (16) on the test board. The deformation ensures a low resistance electrical path between the balls and the pads during testing of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.