Tunnel-junction structures and methods
US6821848B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2002 |
| Grant date | Nov 23, 2004 |
| Priority date | — |
| Expiry date | Nov 22, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Tunnel-junction structures are fabricated by any of a set of related methods that form two or more tunnel junctions simultaneously. The fabrication methods disclosed are compatible with conventional CMOS fabrication practices, including both single damascene and dual damascene processes. The simultaneously formed tunnel junctions may have different areas. In some embodiments, tub-well structures are formed with sloped sidewalls. In some embodiments, an oxide-metal-oxide film stack on the sidewall of a tub-well is etched to form the tunnel junctions. Memory circuits, other integrated circuit structures, substrates carrying microelectronics, and other electronic devices made by the methods are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.