Flip-chip interconnected with increased current-carrying capability
US6822327B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2003 |
| Grant date | Nov 23, 2004 |
| Priority date | — |
| Expiry date | Jun 13, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A metal runner that improves the current-carrying capability of solder bumps used to electrically connect a surface-mount circuit device to a substrate. The runner comprises at least one leg portion and a pad portion, with the pad portion having a continuous region and a plurality of separate electrical paths leading to and from the continuous region. The electrical paths are delineated in the pad portion by nonconductive regions defined in the pad portion, with at least some of the nonconductive regions extending into the leg portion. The multiple electrical paths split the current flow to and from the solder bump, distributing the current around the perimeter of the solder bump in a manner that reduces current density in regions of the solder bump where electromigration is most likely.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.