Method for calibrating threshold levels on comparators with dithered DC signals
US6822485B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 14, 2002 |
| Grant date | Nov 23, 2004 |
| Priority date | — |
| Expiry date | Oct 6, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved method for calibrating threshold voltage levels on comparators corresponds to providing a dithered DC signal to one input and adjusting the threshold voltage on the other input in response to the comparator output. Such calibration may be necessary for comparator circuitry associated with measurement devices. A circuit to generate a dithered DC signal sums a precise DC value with a time-varying signal that has been modified, such as a rectified AC signal. During the calibration procedure, the internal threshold voltage is varied until no timing measurements are present. The difference between the determined optimum threshold voltage and the ideal voltage is stored in a system computer associated with the measurement device and used later in the measurement process to produce a precise threshold voltage input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.